Project Engineer (Detector Electronics, FPGA and VLSI) for the CMS Experiment at CERN, TIFR Mumbai

Job Description

TIFR’s Department of High Energy Physics is hiring a Project Engineer for India’s participation in the CMS experiment at CERN. The engineer will design and debug low-noise analogue front-end circuits and FPGA-based digital readout for particle detectors, and support CMS detector operations. The principal investigators are Dr. Rajdeep Mohan Chatterjee and Dr. Shilpi Jain. The last date to apply is 30 September 2026.

At a glance

• Position: Project Engineer (1 post), Advertisement No. 2026/26
• Project: Indian participation in the CMS experiment at CERN: Maintenance, Operation and Upgradation 2020-2025 (title as given in the advertisement)
• PIs: Dr. Rajdeep Mohan Chatterjee and Dr. Shilpi Jain, Department of High Energy Physics
• Pay: Rs 60,000 per month, consolidated
• Age limit: 29 years on the closing date
• Apply by: 30 September 2026 (by email)

CMS (the Compact Muon Solenoid) is one of the large general-purpose particle detectors at CERN’s Large Hadron Collider, and TIFR is part of the Indian group that helps build, run and upgrade it. This post is on the electronics side: readout systems that take signals from detector sensors, digitise them and move the data at high speed to acquisition systems.

What the project engineer will do

• Design, simulate and debug low-noise analogue front-end circuits for particle detector readout
• Develop and validate high-speed digital and VLSI systems using CPLDs and FPGAs
• Write and maintain firmware in hardware description languages (Verilog, with Vivado)
• Build and test high-speed data links for detector data acquisition, and program soft processors in FPGA-based readout
• Work with physicists and engineers on PCB design and board bring-up
• Support CMS detector operations, including on-call hardware maintenance

The advertisement lists the technical skills it has in mind: analogue design (low-noise amplifiers, ADCs, power management), FPGA/CPLD synthesis, timing closure and simulation, Verilog or VHDL with Vivado or Quartus, high-speed interfaces such as LVDS, GbE and PCIe, and PCB tools such as Altium or KiCad with mixed-signal board bring-up.

Eligibility

• B.E. or B.Tech. in Electronics Engineering or Electronics and (Tele)Communications Engineering, with at least 60% aggregate marks
• At least one year of hands-on experience designing and debugging high-speed analogue, digital and VLSI circuits
• Age: up to 29 years on the closing date
• Desirable: data acquisition systems for particle-detector experiments; end-to-end PCB electronics design including layout and bring-up; firmware in Verilog or the Vivado design suite

Selection is by personal interview. The appointment is temporary and not pensionable, and gives no claim to a permanent or temporary post at TIFR during or after the project.

Pay and duration

• Rs 60,000 per month, consolidated
• Initially one year, extendable by up to two more years depending on performance

How to apply

Email a detailed CV, copies of relevant certificates and a short statement of relevant experience to Dr. Rajdeep Mohan Chatterjee (rajdeep.chatterjee@tifr.res.in) and Dr. Shilpi Jain (shilpi.jain@tifr.res.in), with the subject line “Application for Project Engineer (Name of the candidate)”. The CV should contain only: personal details, your final marksheet or degree certificate, a table of your academic history (SSC, HSC, B.E./B.Tech with year, university, subjects and marks) and the names, emails and phone numbers of two referees. The advertisement is Advertisement No. 2026/26 in the Career Notice list on TIFR’s positions page.

Key dates

• Last date for receipt of applications: 30 September 2026
• Selection: personal interview (date to be communicated)

Please read the TIFR positions page (Advertisement No. 2026/26) before applying, and browse more research engineer jobs on ResearchJobs.in.