Principal Engineer, NPU Compiler and Architecture at NXP Semiconductors, Hyderabad
Job Description
This NPU compiler architect job in Hyderabad sits in NXP’s NPU hardware architecture team. You will co-design the hardware and software of future AI inference accelerators. The job mixes compilers, performance modeling and chip architecture.
At a glance
- Position: Principal Engineer – NPU Compiler & Architecture (full time, requisition R-10061529)
- Where: Hyderabad, India
- Degree: Bachelor’s or Master’s in CS, Computer Engineering, EE or a related field
- Experience: 8+ years in compilers, systems software, computer architecture or AI accelerators
- Apply: open until filled (re-checked 29 October 2026)
What the NPU compiler and architecture engineer does
- Build compiler and software proof-of-concepts for current and next-generation NPUs
- Develop graph lowering, intermediate representations, operator mapping, scheduling, tiling, fusion, memory planning and code generation
- Give software-driven feedback on the compute architecture, memory hierarchy, dataflow and instruction set
- Analyse AI workloads for bottlenecks such as quantization, sparsity, tensor layouts and memory bandwidth
- Build performance models, simulators or emulators for designs that may be months or years from silicon
- Take part in architecture reviews and mentor engineers
Why this role matters
An AI accelerator is only as fast as its compiler lets it be. Here the software is designed alongside the hardware, so your experiments decide which features go into NXP’s future chips before any RTL is written.
What NXP is looking for
- Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electrical Engineering or a related field
- 8+ years of experience in compiler development, systems software, computer architecture, AI accelerators or a close area
- Strong knowledge of compiler architecture and optimisation
- Strong C++ and good Python
- Good grasp of computer and accelerator architecture, memory hierarchies and data movement
- Experience analysing AI/ML workloads and their performance limits
Nice to have
- Compilers or software stacks for NPUs, GPUs, DSPs or TPUs
- MLIR, LLVM, TOSA, StableHLO or Torch-MLIR
- Accelerator scheduling, tiling, memory management or code generation
- NPU concepts such as dataflow, tensor engines, systolic arrays, local SRAMs and DMA
Pay and location
The posting does not state pay. It is a full-time role based in Hyderabad.
How to apply
Apply through the official NXP job posting. NXP’s posting does not give a closing date, so the role is open until filled; ResearchJobs.in will re-check this listing on 29 October 2026. Check the posting for location and work-authorisation details before you apply.
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Hiring institution: NXP Semiconductors
Official advertisement: nxp.wd3.myworkdayjobs.com
How to prepare for this application
- Prepare to walk through a compiler pass you built: the IR, the transformation and the speed-up you measured
- Revise tiling and scheduling for convolutions and matrix multiplies on a memory-limited accelerator
- Be ready to reason about roofline limits: when a layer is compute-bound and when it is bandwidth-bound
- Read up on MLIR dialects and on how quantized INT8 models are lowered to hardware
- Think of one hardware feature you would add to an NPU, and how you would prove its value with a workload study
About NXP Semiconductors
NXP Semiconductors is a Dutch chipmaker headquartered in Eindhoven. It makes processors, microcontrollers and connectivity chips for cars, industry and connected devices, and has design centres in India.
