Two JRF Posts in VLSI and ML-Enabled RISC-V SoC Design, IIT Patna (MeitY C2S Project)

Job Description

This VLSI JRF job at IIT Patna is in the Department of Electrical Engineering. The MeitY project builds a machine-learning-enabled RISC-V chip with a LoRa radio for monitoring events in forests. There are two JRF posts, and selected candidates join the PhD programme.

At a glance

• Post: Junior Research Fellow, 2 posts
• Where: Department of Electrical Engineering, IIT Patna, Bihta, Patna
• Pay: ₹37,000 a month as JRF; ₹42,000 a month as SRF (consolidated)
• Duration: 2 years as JRF, then SRF until the project ends
• Apply by: 22 October 2026, by email

The project is “ML Enabled RISC-V based i-LoRa SOC for Forest Event Monitoring” (project no. R&D/SP/EE/MEM/2023-24/908). The Ministry of Electronics and Information Technology (MeitY) funds it under its Chips to Startup (C2S) programme. Its research areas are VLSI architectures for edge computing, communication systems and machine learning. The advertisement is R&D/908/MEM/631. The notice page dates it 29 September 2026, and the PDF dates it 30 September 2026. The project runs for two years and may be extended by one year. The contact for applications is Dr. Kailash Chandra Ray, Department of Electrical Engineering.

About the RISC-V SoC project

• Work on VLSI architecture for an edge-computing chip built around a RISC-V processor
• Help add machine-learning and LoRa communication blocks to the system-on-chip
• Use EDA tools for design, simulation and verification
• Do a PhD in VLSI and embedded systems alongside the project work

The advertisement gives the research domain but no task list. The points above describe typical JRF work on a project with this title. Ask about the exact tasks at interview. The ad says it wants only candidates who are willing to do a PhD in VLSI and embedded systems.

Why this role matters

India’s chip design push under MeitY’s C2S programme needs people who can take a design from idea to silicon. This JRF combines a RISC-V core, a LoRa radio and machine learning on one chip. It also leads to a PhD in VLSI at IIT Patna.

Eligibility

• M.Tech, B.Tech or M.Sc. in Electrical, Electronics, Communication, Instrumentation or Computer Science and Engineering
• Desired route 1: M.Tech in VLSI, Embedded Systems, Microelectronics, Electronics Systems, Communication Systems, Instrumentation or CSE, with CPI 6.5 or 60%, and a qualified GATE score from the last five years
• Desired route 2: B.Tech, B.Sc. (Engg.) or M.Sc. in the same fields, with CPI 7.5 or 70%, and a qualified GATE score from the last five years
• GATE is waived for B.Tech graduates of IITs with CPI 7.5 or above
• Candidates without GATE but with experience in the field are considered for the JRF post only
• M.Tech holders with two years of relevant experience may be offered SRF directly, based on the interview
• Upper age limit on the date of the ad: 32 years (M.Tech) and 28 years (B.Tech, B.Sc. Engg. or M.Sc.)

Experience in VLSI and embedded systems, computer architecture, communication systems or machine learning, and exposure to EDA tools, gets preference. Age relaxation for SC/ST/OBC/women/PD candidates follows Government of India rules. Selected candidates are admitted to the PhD programme in Electrical Engineering. The ad says “Spring-2026”, which seems to be an error, since that term has passed; check the intake with the department.

Pay and duration

• JRF: ₹37,000 a month (consolidated)
• SRF: ₹42,000 a month (consolidated)
• The ad does not mention HRA
• Post: 2 years as JRF, then SRF until the project ends

How to apply

Fill in the application form attached to the advertisement. Email a scan of it, your GATE score card and a resume that shows your experience in the project’s field to kcr@iitp.ac.in by 22 October 2026. Bring original certificates, mark-sheets and the GATE score card to the interview.

Key dates

• Last date to email the application: 22 October 2026
• Shortlisted candidates told by email: 23 October 2026
• Written test and interview: 3 November 2026, 10 am, Department of Electrical Engineering, IIT Patna, Bihta
• Second-class train fare by the shortest route is paid for the interview; a hostel guest room can be arranged for up to two days on request

Please read the official IIT Patna notice for advertisement R&D/908/MEM/631 before applying, and browse more Junior Research Fellow jobs on ResearchJobs.in.