Senior AI/ML Hardware Architect (TPU), Google Cloud, Bengaluru

Job Description

This AI hardware architect job in Bangalore is with Google’s TPU team in Google Cloud. You will define and explore the architecture of next-generation TPU chips. You will build power and performance models and co-design the hardware with software, compiler and research teams.

At a glance

• Position: Senior AI/ML Hardware Architect, Google Cloud (full time)
• Where: Bengaluru, Karnataka, India
• Degree: Bachelor’s in EE, computer engineering, CS or related, or equal practical experience; a Master’s or PhD is preferred
• Experience: 8 years in architecture and microarchitecture of ML, graphics, fabric, numerics, vector or DSP processors, or networking ASICs
• Posted: 19 October 2026
• Apply: open until filled (re-checked 19 November 2026)

What the TPU hardware architect does

• Write architecture specifications for Google’s AI/ML hardware roadmap
• Build architectural and microarchitectural power and performance models, and analyse the results
• Own the microarchitecture of compute blocks and subsystems
• Co-design hardware and software with design, compiler, ML model and research teams
• Evaluate silicon options for Google’s data centre AI accelerators, including vendor co-development, custom designs and chiplets
• Drive power, performance and area gains, and help build simulation tools

Why this role matters

TPUs run Google’s largest AI models. Each new generation must do more work per watt. The architect decides what the next chip should look like, long before it is built. The posting calls this “definition and path-finding”, which is the research end of chip design.

What Google is looking for

• Bachelor’s in electrical engineering, computer engineering, computer science or a related field, or equal practical experience
• 8 years in architecture and microarchitecture of graphics or ML processors, scale-up/out fabrics (Ethernet, RoCE, UAL, NVLink), low- or mixed-precision numerics, vector or DSP processors, or networking ASICs
• Experience with on-chip memory hierarchy, fabrics, memory controllers, HBM and DRAM

Nice to have

• Master’s or PhD in computer engineering, electrical engineering or equal practical experience
• Experience optimising the hardware/software interface with software teams
• Performance analysis and modelling, and defining performance test plans
• C++ and Python
• Knowledge of arithmetic units, bus architectures, accelerators, memory hierarchies and low-power design

Pay and location

The posting does not state pay. The role is based in Bengaluru. Google says most hires for this role need in-person interviews.

How to apply

Apply through the official Google job posting. Google’s posting does not give a closing date, so the role is open until filled; ResearchJobs.in will re-check this listing on 19 November 2026. Check the posting for location and work-authorisation details before you apply.

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