DFT Design Engineer (Scan, ATPG, MBIST) at Intel (Bengaluru, Contract)
Job Description
Intel in Bangalore is hiring a DFT (design-for-test) Design Engineer with two or more years of experience. The work covers scan architecture, ATPG and fault models, JTAG, memory BIST and repair, and DFT verification with timing-annotated gate-level simulation. Note that the posting lists this as an Intel contract employee role, with Intel’s hybrid work model.
At a glance
- Role: DFT Design Engineer (req. JR0286726)
- Location: Bangalore, India (hybrid)
- Experience: B.E./B.Tech/M.E./M.Tech with 2+ years of DFT
- Type: Intel contract employee
- Apply: open until filled (re-checked 14 October 2026)
What you would do
- Work on scan architecture (SSN topology), ATPG and fault models using Spyglass DFT
- Implement JTAG, memory BIST and memory repair (BIRA/BISR) circuits
- Verify DFT with timing-annotated gate-level simulations
- Debug DFT problems, simulation failures, coverage gaps and DRCs, and support post-silicon ATE teams
Why this role matters
Every chip must be tested after manufacturing, and DFT engineers build the test structures that make that possible and affordable. It is one of the most in-demand VLSI specialisations in India, and this role is open to engineers with just two years of experience.
What Intel is looking for
- A B.E./B.Tech/M.E./M.Tech in electrical, electronics or communication engineering with 2+ years of DFT
- Knowledge of Spyglass DFT, scan, ATPG and fault models
- RTL coding and shell scripting
- Understanding of timing constraints and DFT-mode timing
Nice to have
- Experience with post-silicon and ATE debug
Pay and location
Intel does not publish a salary in this ad. It is listed as an Intel contract employee position, so check the terms with the recruiter.
How to apply
Apply through the official Intel job posting. Intel’s posting does not give a closing date, so the role is open until filled; ResearchJobs.in will re-check this listing on 14 October 2026. Check the posting for location and work-authorisation details before you apply.
See all our industry R&D jobs, or browse more research jobs on ResearchJobs.in.
Hiring institution: Intel
Official advertisement: intel.wd1.myworkdayjobs.com
How to prepare for this application
- Name your tools: Spyglass DFT and ATPG tools you used.
- MBIST and repair: BIST or repair circuits you implemented stand out.
- Gate-level debug: show simulation failures you solved.
- Contract role: ask about duration and conversion.
About Intel
Intel designs and manufactures processors and other silicon. Its Bangalore campus is one of its biggest design centres, covering CPU, SoC and IP design, verification and test.
