Job Description
Intel in Bangalore is hiring a Component IP RTL Design Engineer for its Unified Chassis designs, focused on protocol bridges that convert between interconnects such as AXI, AXI-Lite, APB and Intel’s own sideband and fabric interfaces. The work covers micro-architecture, RTL, access control and error handling, with room to contribute to other IP blocks.
At a glance
- Role: IP RTL Design Engineer (req. JR0284060)
- Focus: Protocol bridge IP for Intel Unified Chassis
- Location: Bangalore, India
- Posted: 9 September 2026
- Apply: open until filled (re-checked 14 October 2026)
What you would do
- Design, implement and verify protocol bridges between AXI, AXI-Lite, APB, IOSF-SB, HBW and LBW interfaces
- Define micro-architecture and interface requirements with architects
- Write RTL and simulations for correctness and performance
- Implement access control, privilege checks and policy propagation for secure data paths
- Support error detection, parity/ECC and transaction error handling
Why this role matters
Protocol bridges let blocks built for different on-chip interconnects talk to each other safely. In a modular ‘chassis’ approach, where Intel reuses standard building blocks across products, these bridges and their security and error handling are what hold a chip together.
What Intel is looking for
- A degree in electrical or computer engineering
- RTL design experience in SystemVerilog or Verilog
- Good knowledge of on-chip bus protocols such as AXI and APB
- Ability to work from micro-architecture to verified RTL
Nice to have
- Experience with secure data paths, ECC or error handling in interconnect IP
Pay and location
Intel does not publish a salary in this ad; pay depends on experience and grade. The role is based in Bengaluru, India; check the posting for the exact site and any hybrid working arrangement.
How to apply
Apply through the official Intel job posting. Intel’s posting does not give a closing date, so the role is open until filled; ResearchJobs.in will re-check this listing on 14 October 2026. Check the posting for location and work-authorisation details before you apply.
See all our industry R&D jobs, or browse more research jobs on ResearchJobs.in.
Hiring institution: Intel
Official advertisement: intel.wd1.myworkdayjobs.com
How to prepare for this application
- Protocols first: list AXI, APB or other interconnects you designed logic for.
- Show micro-architecture: a block you specified before coding.
- Security and errors: access control or ECC work matches this role well.
- Verification: say how you tested your RTL.
About Intel
Intel designs and manufactures processors, chipsets and other silicon, and runs a foundry business. Its Bangalore campus is one of the company's largest design centres, with teams across CPU, SoC and IP design, verification and physical design.