Principal Engineer, Agentic AI for Chip Design (CAD/EDA), Synopsys, Bengaluru
Job Description
This AI for chip design job in Bangalore is a principal engineer role in Synopsys’ AI Centre of Excellence. You will build AI agents that work with chip design tools. The aim is to automate design and verification tasks for Silicon Lifecycle Management (SLM) IP.
At a glance
- Position: Principal Engineer, Agentic AI (CAD/EDA) (full time, job ID 18373)
- Where: Bengaluru, India
- Team: Silicon Lifecycle Management IP Development, AI Centre of Excellence
- Degree: Bachelor’s, Master’s or PhD in computer science, VLSI, electrical engineering or a related field
- Experience: 12+ years building and deploying advanced CAD flows in silicon design
- Posted: 28 September 2026
- Apply: open until filled (re-checked 12 November 2026)
What the agentic AI principal engineer does
- Architect AI-powered CAD infrastructure for silicon IP, with autonomous agents built into design and verification
- Build agent frameworks and agents that raise engineering productivity
- Connect LLMs, agents and EDA tools across design, verification, synthesis, place-and-route and timing
- Design multi-agent workflows that automate IP design tasks, verification loops and lifecycle analytics
- Prototype and test new AI-CAD links in live projects, and improve them from designers’ feedback
- Set the technical roadmap for AI-assisted CAD in SLM, and mentor the team
Why this role matters
LLM agents are new in chip design, and few teams have made them work on real silicon. This role defines how Synopsys, one of the main EDA vendors, uses them inside its own IP development. The posting says it may grow into leading a small team.
What Synopsys is looking for
- Bachelor’s, Master’s or PhD in computer science, VLSI, electrical engineering or a related field
- 12+ years developing and deploying advanced CAD flows and infrastructure in silicon design
- Production experience with agent frameworks such as LangGraph, AutoGen or CrewAI, or LLM orchestration
- Strong Python and C++, plus Tcl, Perl and shell scripting
- A record of building agents that work with design, verification, synthesis, place-and-route and timing flows
Nice to have
- Knowledge of IP development, verification and lifecycle management
- Silicon Lifecycle Management concepts such as in-chip sensing, telemetry and analytics (a strong plus)
Pay and location
The posting does not state pay. Synopsys says the recruiter will share the salary range and benefits during hiring. The role is based in Bengaluru.
How to apply
Apply through the official Synopsys job posting. Synopsys’s posting does not give a closing date, so the role is open until filled; ResearchJobs.in will re-check this listing on 12 November 2026. Check the posting for location and work-authorisation details before you apply.
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Hiring institution: Synopsys
Official advertisement: careers.synopsys.com
How to prepare for this application
- Prepare a case study of one CAD flow you built that designers adopted: the problem, the design and the time it saved
- Show a working agent you built with LangGraph, AutoGen or similar, and explain how you kept it reliable
- Be ready to discuss where LLM agents fail on EDA tasks, and how you would check their output
- Revise the full IP flow from RTL to timing sign-off, so you can say where agents help most
- Read Synopsys' public material on Silicon Lifecycle Management and in-chip monitors
About Synopsys
Synopsys is a US company that makes electronic design automation (EDA) software, semiconductor IP and simulation tools for chip and system design. It has large R&D centres in India, including in Bengaluru.
