Job Description
IonQ is hiring a Photonic Layout Engineer for the QPU Design team at Oxford Ionics/IonQ, based in College Park, Maryland or Oxford, UK, to lay out the photonic integrated circuits that bring light onto the chip in its trapped-ion quantum processors.
At a glance
- Role: Photonic Layout Engineer, QPU Design team
- Where: College Park, Maryland, USA, or Oxford, England, UK
- Experience: significant PIC design and layout experience; 2+ years with Python mask-layout tools
- Level: degree in photonics, physics, electrical engineering or similar, or equivalent industry experience
- Apply: open until filled (re-checked 11 October 2026)
About the photonic layout role
- Arrange and route photonic components on the chip, coordinating with metal tracks and CMOS routing
- Produce reticle-size photonic layout files with Python scripts as part of tapeouts
- Discuss requirements with scientists, and work with photonic designers, test, packaging and fabrication engineers to define design rules and shape components
- Verify layouts through DRC and LVS checks
- Contribute to custom process design kits (PDKs) specific to IonQ and its foundry
- Document the layout process and the final tapeout mask files
Delivering laser light through waveguides built into the chip, rather than through bulky free-space optics, is one of the ways trapped-ion processors can scale to thousands of qubits. This role integrates those photonic components into complex multi-layer chips, alongside metal tracks and CMOS routing.
What IonQ is looking for
- Proficiency in photonic integrated circuit layout
- Understanding of photonic devices such as waveguides, beamsplitters and grating couplers, including their design, testing and fabrication
- At least 2 years with Python packages for photonic mask layout, such as Luceda IPKISS, GDSFactory or KLayout
- A degree in photonics, physics, electrical engineering or a related field, or equivalent industry experience
- Strong collaboration and communication, and the ability to work independently and prioritise under time pressure
Nice to have
- Generating layout files for photonic or complex semiconductor devices, especially with custom elements
- Knowledge of manufacturing processes and techniques
Pay and location
IonQ’s posting does not state a salary. The role can be based in College Park, Maryland, USA, or Oxford, UK.
How to apply
Apply through the official IonQ job posting. IonQ’s posting does not give a closing date, so the role is open until filled; ResearchJobs.in will re-check this listing on 11 October 2026. Check the posting for location and work-authorisation details before you apply.
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Hiring institution: IonQ
Official advertisement: job-boards.greenhouse.io
How to prepare for this application
- Show a layout: bring screenshots or a repository of a scripted PIC layout you produced, with the design rules it had to meet.
- Multi-layer thinking: be ready to discuss how photonic layers interact with metal routing: crosstalk, heating and spacing rules.
- Verification: explain your DRC and LVS workflow and how you track down violations.
- Ion-trap specifics: trapped ions use visible and ultraviolet light, so read up on the waveguide materials used at those wavelengths.
- Documentation: mention how you keep tapeout records clear for fabrication teams.
About IonQ
IonQ, Inc. (NYSE: IONQ) builds trapped-ion quantum computers and describes itself as a quantum platform company working across computing, networking, sensing and security. It is headquartered in College Park, Maryland, with operations in several US states and in Italy, South Korea, Sweden, Switzerland, Canada and the United Kingdom.