Analog Mixed-Signal Lead Design Engineer (SerDes) at Cadence, Bengaluru
Job Description
This SerDes analog design job in Bangalore is with Cadence. You will design high-speed, low-power SerDes transceivers for data centres, networking, AI and high-performance computing. It is a T3 lead design role.
At a glance
- Position: Lead Design Engineer: Analog Mixed-Signal Lead Design Engineer (T3) – SerDes (full time, requisition R56130)
- Where: Bengaluru, India
- Experience: B.S. with 3+ years, or M.S. with 1+ years
- Closes: 31 October 2026
- Apply: 31 October 2026 (the end date shown on the posting)
What the SerDes lead design engineer does
- Design and verify SerDes blocks: TX drivers, serializers, RX front ends, CTLEs, samplers and comparators
- Work on ADCs, DACs, PLLs, DLLs, clock distribution, regulators, bias circuits and calibration loops
- Turn link-level needs into circuit specifications and optimise across PVT, mismatch, aging and parasitics
- Build behavioural models and support mixed-signal and top-level verification
- Work with layout and signal-integrity teams on post-layout sign-off
- Support tapeout, silicon bring-up, characterization, debug and production release
Why this role matters
AI clusters move huge amounts of data between chips, and SerDes links carry most of it. Faster, lower-power links let more compute work together. The experience bar is low for a lead role, so a recent M.S. graduate can apply.
What Cadence is looking for
- B.S. in Electrical Engineering or a related field with 3+ years of relevant experience, or an M.S. with 1+ years
- Strong analog CMOS, noise, jitter, feedback, signal-integrity and data-converter basics
- Hands-on transistor-level design of high-speed SerDes circuits
- Strong command of Cadence Virtuoso, Spectre, Spectre RF, ADE, parasitic extraction and mixed-signal verification
Nice to have
- PAM4/NRZ SerDes, FinFET nodes, and standards such as Ethernet, PCIe or CXL
- MATLAB or C for architecture work, SystemVerilog or Verilog-A for models, Perl or Python for automation
- Responsible use of AI-assisted engineering tools
- Custom analog layout and lab characterization
Pay and location
The posting does not state pay. It is a full-time role in Bengaluru. The posting shows an end date of 31 October 2026.
How to apply
Apply through the official Cadence page. The closing date is 31 October 2026 (the end date shown on the posting).
See all our industry R&D jobs, or browse more research jobs on ResearchJobs.in.
Hiring institution: Cadence Design Systems
Official advertisement: cadence.wd1.myworkdayjobs.com
How to prepare for this application
- Revise CTLE and DFE equalisation, and how you budget jitter across a SerDes link
- Be ready to size a CML driver or a StrongARM comparator on a whiteboard and explain the trade-offs
- Explain PAM4 versus NRZ: eye height, SNR penalty and why PAM4 is used at 56 Gb/s and above
- Bring numbers from a circuit you taped out or simulated: bandwidth, power, noise and area across corners
- Review how PLL phase noise turns into jitter, since clocking questions come up in almost every SerDes interview
About Cadence
Cadence Design Systems is a US company that makes electronic design automation software and semiconductor IP used to design chips. It has large R&D centres in India, including Bengaluru and Noida.
