Senior Photonic Layout Design Engineer (Silicon Photonics and SerDes) at NVIDIA, Santa Clara
Job Description
NVIDIA is hiring a senior photonic layout design engineer in Santa Clara to own the physical design and verification of photonic integrated circuits, from proof of concept to high-volume manufacturing. The engineer lays out waveguides, modulators, photodetectors and mixed-signal blocks, drives tape-outs including floor planning, waveguide routing and mask preparation, builds test structures with large design-of-experiment arrays, and develops AI-assisted layout automation and custom PCells.
At a glance
- Role: Senior Photonic Layout Design Engineer (JR2017453)
- Location: Santa Clara, California, USA
- Posted: 8 September 2026
- Experience: 12+ years of full-chip layout
- Pay: $148,000 to $235,750 (Level 5); $176,000 to $276,000 (Level 6)
- Apply: open until filled (re-checked 13 October 2026)
About the photonic layout role
- Lead manual and automated layout of waveguides, modulators, photodetectors, I/Os and ESD structures
- Drive tape-outs: floor planning, waveguide routing and mask data preparation
- Run DRC, LVS, fill and density checks and fix layout-dependent issues
- Lay out test vehicles with large DOEs for process windows
- Develop AI-assisted methods, layout scripts and custom PCells
What NVIDIA values here
The posting stresses a deep understanding of advanced semiconductor fabrication, strong automation skills and a record of first-time-right high-density designs, plus working with integration and design-rule teams to reach high manufacturing yield.
What NVIDIA is looking for
- A BS, MS or PhD in electrical engineering, physics or a related field
- 12+ years of hands-on full-chip layout in semiconductor, analogue or silicon photonics
- Analogue layout and silicon photonic constraints in advanced CMOS and SiPh processes
- Cadence Virtuoso and Calibre, ICV or similar verification
- Python, SKILL, Perl, Tcl or C++ for automation
Pay and location
NVIDIA lists base salary ranges of $148,000 to $235,750 at Level 5 and $176,000 to $276,000 at Level 6, plus equity and benefits.
How to apply
Apply through the official NVIDIA job posting. NVIDIA’s posting does not give a closing date, so the role is open until filled; ResearchJobs.in will re-check this listing on 13 October 2026. Check the posting for location and work-authorisation details before you apply.
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Hiring institution: NVIDIA
Official advertisement: nvidia.wd5.myworkdayjobs.com
How to prepare for this application
- Curvy layouts: show how you handle curved waveguides in DRC flows.
- Automation: bring scripts or PCells that saved layout time.
- DOEs: describe a test vehicle you laid out and what it measured.
- Timing: the minimum application window ended 12 September 2026; the role is still listed.
About NVIDIA's photonics work
NVIDIA builds GPUs and networking for AI supercomputers. Its photonics teams develop silicon photonic chips and co-packaged optical interconnects that move data between processors using light.
